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Graphene technique for detachable, flexible opto and microelectronic devices, with repeated substrate reuse



Semiconductor technologies are integral to all modern devices. This invention is a novel method performed on semiconductor wafers enabling easy material hetero integration, device detachment, as well as the multiple reuses of the substrate. This original approach, called Anchor Point Nucleation (APN), presents a groundbreaking method for heteroepitaxy, the layer deposition of various semiconductor materials without the constraints of conventional techniques, to create high-performance devices. The key advantage of this method is that any crystalline material such as Silicon or Germanium can be used as the substrate without limitations of lattice matching with deposited material, thanks to the relaxation of the 2D interface. Moreover, the final epitaxial structure can be detached from the substrate enabling its repeated reuse, thus significantly reducing device costs. 

This invention aims to revolutionize electronic technologies enabled by this new approach. It will lead to a new generation of high-performance, flexible, and multifunctional devices based of freestanding membrane structures and/or hybrid 3D/2D (semiconductor/graphene) heterostructures, pushing the boundaries of electronics to the next level. These hybrid heterostructures can profoundly impact various sectors, including healthcare, telecommunications, energy production, quantum computing and defense (secure communications and radars).


The method, illustrated in Figure 1, consists of the following steps:
- Depositing a layer of graphene (so thin, only 1 atom thick, that it is considered “2D”).
- Creating nucleation sites in the graphene by controlled introduction of defects (vacancies, nano-holes, interstices, etc.). These defects act as preferential nucleation sites during epitaxy, anchoring the semiconductors on the substrate and forming a substrate-oriented crystalline seeding layer.
- Growing devices on the graphene through epitaxy, involving successive layer deposition.
- Detaching the device heterostructure from the substrate and transferring it to another substrate of interest.
- Reconditioning the substrate for repeated reuse. 

For more details, see : Unraveling the Hetero integration of 3D Semiconductors on Graphene by Anchor Point Nucleation, Small 2024, 20, 2306038.


  • A universal method allowing the growth of monocrystalline layers on polar and non-polar substrates; a first in the field.

  • The use of a 2D graphene interface, resolving constraints related to crystal mismatches between the substrate and epitaxial layer, a fundamental problem in heteroepitaxy.

  • Improves the wettability and reactivity of the graphene interface, addressing the fundamental problem of Van der Waals epitaxy: the low surface energy of graphene.

  • Enables layer detachment: The weak bonding between the heterostructure and 2D interface allows for an easy detachment.

  • This method allows for precise control of the thickness of the layer to be transferred, with lower stress.

  • In comparison to existing techniques:

    • Does not require sacrificial layers, eliminating the need for etching to detach the layer.

    • Applicable at large scale, unlike most current methods limited to small areas.

    • Improves on the limitations of existing techniques regarding layer transfer.

  • Significantly reduces the cost of devices, as the substrate accounts for a big part of the fabrication costs:

    • E.g. – In 2016, the semiconductor industry spent more than $7 billion on wafers used as substrates for transistors, LEDs, and other devices. The substrate is used in its entirety while less than 5% of its thickness plays an active role in device functionality.

    • In contrast, this method reuses the substrate, enabling the use of rare materials as substrate, without worrying about substrate costs (2-3 orders of magnitude more expensive than Silicon). Result: devices up to 5X cheaper.



  • High performance hybrid devices (3D/2D)

  • Flexible electronics and optoelectronics

  • Hetero integration with complementary metal oxide semiconductor (CMOS) technology

  • Development and mass fabrication of ultra-flexible devices in several domains:

    • Mobile telecommunications and the Internet of Things (IoT)

    • Energy production – photovoltaic and thermophotovoltaic cells

    • Photonics – Lasers on Silicon; Optical communications

    • Light-emitting diodes (LEDs) and photodetectors, Quantum technologies

    • Healthcare – On-skin and wearable medical devices.​

  • Market

    • Among several other applicable markets for this invention, the optoelectronics devices market is projected to reach US$52.7 billion in 2025, growing at 5% per year; with these verticals: automotive, military and aerospace, medical, consumer electronics, commercial, telecommunications, industrial and residential.



  • TRL 2-3: Proof of concept demonstrated, and prototype developments are in progress.


  • Patent applications filed.


  • Commercial partners

  • Development partners 

  • Investments

  • Licences

  • Start-up

Project Director: François Nadeau

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