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Denser microelectronic chip assembly – enabling 3D chip integration



The world of microelectronics is constantly evolving. Thanks to Moore's law, the constant technological evolution allows the miniaturization of semiconductor devices. Nowadays, we all continuously exploit such devices in our smart phones, tablets, GPS and many more. The latter offer us more and more functionalities each year thanks to the continuous miniaturization of integrated circuits into microelectronic chips. 

These devices are the subject of the present invention, more specifically the high-density interconnection of an inverted electronic chip (“flip chip”) directly with its substrate during its encapsulation (vs. connection by wire). This innovative idea gives rise to various improvements both in terms of the reliability of the chip assembly process and in the reduction of the costs involved.


This innovation is based on the creation of new weld pillars manufactured via a sequential electrodeposition approach at the wafer level where layers acting as barriers are integrated at the level of the weld structure in order to locally control the many characteristics of the weld. alloy between tin and silver (SnAg). 

Therefore, each pillar is a heterogeneous structure composed of a complete envelope of tin (Sn) as well as a nickel (Ni) barrier, making it possible to limit the diffusion of silver (Ag) between the two segments. This method makes it possible to form a structure comprising an alloy with a low Ag content so that the joint is more ductile on the side of the fragile layers of the chip, and thus reduces the local thermomechanical stresses caused by the pillar during assembly. Once the various constraints of the assembly have been mitigated by the ductile alloy, the latter is reinforced with a filling resin. 

The invention also provides a means to easily break this barrier in order to homogenize the weld pillar at the appropriate time, which allows an even distribution of Ag in the structure. The purpose of this homogenization is to improve the resistance of the solder to electromigration (the movement of material in the bump).

Furthermore, the pillar-like structure has the added benefit of ensuring a high aspect ratio that allows for a high-density interconnect design without the use of a rigid copper (Cu) structure. This Ni wrapping concept can be used to avoid the high rigidity of the copper micropillar for high density connections. These new tin micropillars will address the 3D integration market in microelectronics.

Current industrial processes use consistent solder bumps throughout the design, requiring the selection of a single alloy that serves as a compromise between good thermomechanical performance and good resistance to electromigration. This invention eliminates the need to neglect one of the two aspects, thus prolonging the integrity of the microelectronics.



  • Improved thermomechanical performance of the assembly while maintaining high resistance to electromigration (higher aspect ratio).

  • Improved pillar geometry compared to the more spherical conventional structure — allows for higher density and fewer solder bridges (electrical shorts).

  • Innovation in the manufacturing process and the structure of the resulting pillar-like bumps. Current processes use homogeneous bumps, with a single alloy.

  • Current processes use homogeneous bumps, with a single alloy. 

  • Suitable for all aspect ratios.

  • Controls the diffusion of Ag.

  • Creates a pillar-like structure, made entirely of solder to improve assembly of high-density chips without the need for rigid copper pillars that are highly stressed.

  • Enables 3D integration — “stacking” of components to create increased performance (shorter interconnect lengths) using less space (XY).

  • A higher aspect ratio (height/diameter) offers two advantages: 

  • Greater height provides more space between the chip and the substrate, facilitating any necessary cleaning of solder flux residue and facilitating the penetration of filler resin applied later. 

  • A smaller diameter reduces the likelihood of weld bridges.


  • Low-cost manufacturing approach through:

  • Less expensive galvanizing materials (plating solutions);

  • Easier control of the electroplating process

  • Increased product yields

  • Improved product reliability. 

  • Copper-free pillars as a solution to increase interconnect density.


  • Encapsulation of microelectronic chips. 



  • For abutments no bump of 150 um or more — TRL 5-6

  • The proof of concept is done. The technology is ready for collaboration and transfer to industry to mature from TRL 5-6 to TRL 9.

  • Pursue development in order to find industrial partners and optimize the method to their respective environments and practices as well as negotiate operating licenses. 

  • Developments to come during the year — TRL 5-6 to TRL 6: 

  • Optimization of the manufacturing process and improvement of reproducibility to industrial standards; method scaling.

  • Assessing reliability and developing improvements.

  • Realization of a functional and marketable product for the partners.

  • Obtaining certification.

  • For micropillars no bump less than 150 um and typically between 40 and 50 um) — TRL 2-3

  • Demonstrate the possibility of replacing copper micropillars with tin micropillars, which would address the 3D integration market in microelectronics (higher density).


  • Patent application filed.


Development partners. Investments. Licenses. 

Project Director: François Nadeau

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